1. Technical Field
The present disclosure relates to a path data transmission unit, and more particularly, to a path data transmission unit that transmits normal data and test data in a normal mode and a test mode, respectively, through two separate output terminals wherein one of the two data types concurrently transmitted from the two output terminals has a predetermined voltage level.
2. Discussion of the Related Art
Circuits that are designed to externally monitor data processed internally in function blocks or data transferred between function blocks have an advantage in that checking the operational status of the function blocks and detecting the function blocks having an error can be easily performed later on, without disassembling a wafer or a package.
In most digital systems, a plurality of shift registers connected in series is used to transfer and store data, and output data from a plurality of the shift registers connected in series is transmitted to predetermined function blocks. When the system does not operate normally, the place at which the problem occurs should be detected. For such detection, test data is transmitted to a first shift register of the shift registers connected in series and then shifted. Then the test data is transmitted to the function blocks. The operational status of the function blocks can be checked by testing data subsequently transmitted from the function blocks in response to the transmitted input test data. This detection method is called a scan method.
FIG. 1 illustrates a part of a conventional system to which the scan method is applied.
Referring to FIG. 1, the conventional system 100 includes function blocks 140 that perform predetermined functions, and a plurality of shift registers 110,120 and 130.
The first shift register 110 receives normal data ND through a first input terminal D, receives test data TD through a second input terminal TI, stores the test data TD, and transmits the test data TD through an output terminal Q in response to a clock signal CLK. It is determined, based on a test enable signal TE, whether it is a normal mode or a test mode. The first shift register 110 stores and transmits the normal data ND in the normal mode, and stores and transmits the test data TD in the test mode. A second shift register 120 operates in response to an output Q from the first shift register 110. The second shift register 120 operates normally only when the test enable signal TE indicates the test mode, and the other operational characteristics thereof are the same as those of the first shift register 110. A third shift register 130 operates in response to an output signal of a function block 140. The third shift register 130 operates only when the test enable signal TE indicates the normal operation mode, and the other operational characteristics thereof are the same as those of the first shift register 110.
When the test enable signal TE indicates the test mode, the test data TD which is transmitted through the output terminal Q of the first shift register 110 is transmitted to the second input terminal TI of the second shift register 120. When the test enable signal TE indicates the normal mode, the normal data ND which is transmitted through the output terminal Q of the first shift register 110 is transmitted to the function block 140. After being processed by predetermined arithmetic operations, the normal data is transmitted to the third shift register 130.
Hereinafter, the data path formed when the data is transmitted from the output terminal Q of the first shift register 110 to the second input terminal TI of the second shift resister 120 is referred to as a first path Path1, and the data path formed when the data is transmitted from the output terminal Q of the first shift register 110 to the first input terminal D of the third shift resister 130 is referred to as a second path Path2. In addition, the function block to be tested in a test mode is assumed to operate in response to the test data TD transmitted from the output terminal Q of the second shift resister 120, although the connection is not shown in the figure.
It is preferable that, in the test mode, only the first path Path1 is enabled, so that the test data TD is stored in the second shift register 120 and that, in the normal mode, only the second path Path2 is enabled, so that the normal data ND is processed by the function block 140 and stored in the third shift register 130. Referring to FIG. 1, although the third shift resister 130 does not operate in response to the test enable signal TE in the test mode, however, the second path Path2 is activated, so that the function block 140 operates. Therefore, power consumption increases.
FIG. 2 is an internal circuit diagram of the shift resisters 110,120, and 130 illustrated in FIG. 1
Referring to FIG. 2, the normal data ND or the test data TD is selected according to the test enable signal, and the selection operation is performed inside the dotted rectangle. The shift resisters shown in FIG. 2 are constructed with commonly used master-slave type flip-flops, and a description of the method of operation of the shift registers is omitted.
As illustrated in FIG. 1, even though two separate data paths Path1 and Path2 are not used simultaneously, it is not possible to enable only one path due to the structure using the output of the first shift register 110 as a common input of the second and third shift registers.